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M
* PIC16C642 * PIC16C662
PIC16C64X/66X
Pin Diagrams
PDIP, SOIC, Windowed CERDIP MCLR/Vpp RA0 RA1 RA2 RA3 RA4/T0CKI RA5 Vss OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT Vdd Vss RC7 RC6 RC5 RC4
EPROM Memory Programming Specification
This document includes the programming specifications for the following devices:
1.0
PROGRAMMING THE PIC16C64X/66X
PIC16C64X
The PIC16C64X/66X can be programmed using a serial method. In serial mode, the PIC16C64X/66X can be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16C64X/66X devices in all packages.
1.1
Hardware Requirements
PDIP, Windowed CERDIP MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5 RE0 RE1 RE2 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2
The PIC16C64X/66X requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V.
1.2
Programming Mode
PIC16C66X
The programming mode for the PIC16C64X/66X allows programming of user program memory, special locations used for ID, and the configuration word for the PIC16C64X/66X.
Note:
Peripheral pinout functions are not shown (see data sheet for full pinout information).
TABLE 1-1:
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16C64X/66X
During Programming
Pin Name Pin Name RB6 RB7 MCLR/VPP VDD VSS CLOCK DATA VPP VDD VSS Pin Type I I/O P P P Pin Description Clock input Data input/output Programming Power Power Supply Ground
Legend: I = input, O = Output, P = Power
(c) 1997 Microchip Technology Inc.
DS30457A-page 1
PIC16C64X/66X
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
TABLE 2-1:
IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC16C64X/66X
Program Memory Size 0x000 -0xFFF (4K) 0x000 -0xFFF (4K)
The user memory space extends from 0x0000 to 0x1FFF (8K). Table shows actual implementation of program memory in the PIC16C64X/66X microcontroller family. When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (Figure 2-1). In Programming Mode, the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.3. In the configuration memory space, 0x2000-0x20FF or 0x2000-0x20FF are utilized. When in a configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as PC exceeds 0x2XFF (Figure 2-1).
Device PIC16C642 PIC16C662
A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000: 0x2003]. It is recommended that the user use only the six least significant bits of each ID location where the least two significant bits are the parity bits. In some devices, the ID locations read-out in a scrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1666 bbbb pp" where 'bbbb' is ID information. Note 1: All other locations are reserved and should not be programmed. 2: Parity bits must be clocked in/out for identification, but are ignored and not checked. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 4.1.
FIGURE 2-1:
PROGRAM MEMORY MAPPING
4 KW 0000h 2000h 2001h 2002h 2003h 2004h 2005h 2006h 2007h ID Location ID Location ID Location ID Location Reserved Reserved Reserved Configuration Word 1FFFh 207Fh 20FFh 2100h Reserved Reserved 03FFh 0400h 07FFh 0800h 0BFFh 0C00h 0FFFh 1000h Implemented Implemented Implemented Implemented
Reserved
3FFFh
DS30457A-page 2
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
2.2 Program Memory Parity
The PIC16C66X has on-chip parity bits that can be used to verify the contents of the program memory during run time. Parity bits may be useful in applications in order to increase overall reliability of the system. Due to the on-chip parity bits the entire program memory word has been enlarged to 16 bits. The user is responsible to generate and program the correct parity for a given program memory word. The two parity bits are computed on alternating bits of the program word. One computation is performed using even parity, the other using odd parity as shown in Figure 2-2.
FIGURE 2-2:
EPROM MEMORY WITH PARITY CHECKING
E P 10 R 9 O 8 M 7 6 S 5 T 4 I 3 C 2 K 1 S 0 PO PE
13
12
11
ERROR
(c) 1997 Microchip Technology Inc.
DS30457A-page 3
PIC16C64X/66X
2.3 Program/Verify Mode
2.3.1 SERIAL PROGRAM/VERIFY OPERATION The Program/Verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (Hi-impedance inputs). Note: The MCLR pin should be raised as quickly as possible from VIL to VIHH. this is to ensure that the device does not have the PC incremented while in valid operation range. The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled 6 times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time of 100 ns with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay the clock pin is cycled 18 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSb first. Therefore, during a read operation the LSb will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSb will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands. 2.3.2 LOAD CONFIGURATION
After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 18 cycles to the clock pin, the chip will load 16-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL).
TABLE 2-2:
COMMAND MAPPING (SERIAL OPERATION)
Command Mapping (MSb...LSb) XX000X XX001X XX010X XX011X XX100X XX111X Data start_bit, data (16), stop_bit start_bit, data (16), stop_bit start_bit, data (16), stop_bit
Load Data, Set PC = 2000h Load Data for Program Memory Read Data Increment Address Begin Programming End Programming
DS30457A-page 4
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C64X/66X PROGRAM MEMORY
Start
Set VDD = VDDP*
N=0 No Program Cycle N > 25 Yes Report Programming Failure
Read Data Command
N=N+1 N=# of Program Cycles No
Increment Address Command
Data Correct? Yes Apply 3N Additional Program Cycles
Program Cycle No Load Data Command
All Locations Done? Yes Verify all Locations @ VDD min.* VPP = VIHH2
Begin Programming Command
Wait 100 s Data Correct? Yes Verify all Locations @ VDD max. VPP = VIHH2 No Report Verify @ VDD min. Error End Programming Command
Data Correct? Yes Done
No
Report Verify @ VDD max. Error
* VDDP = VDD range for programming. VDDmin = Minimum VDD for device operation. VDDmax = Maximum VDD for device operation.
(c) 1997 Microchip Technology Inc.
DS30457A-page 5
PIC16C64X/66X
FIGURE 2-4: PROGRAM FLOW CHART - PIC16C64X/66X CONFIGURATION WORD & ID LOCATIONS
Start
Load Configuration Command
N=0
No
Program ID Loc?
Yes Program Cycle
Read Data Command
Increment Address Command
N=N+1N=# of Program Cycles
No Data Correct? Yes
No
Address = 2004 Yes
No
N > 25 Yes
Increment Address Command
Report ID Configuration Error
Apply 3N Program Cycles
Increment Address Command
Increment Address Command
Program Cycle 100 Times
Read Data Command
No
Data Correct? Yes
Report Program ID/Config. Error No Done Yes Data Correct?
No
Data Correct? Yes Set VDD = VDDmax Vddmax Read Data Command Set VPP = VIHH2
Set VDD = VDDmin Vddmin Read Data Command Set VPP = VIHH2
DS30457A-page 6
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
2.3.2.1 LOAD DATA
2.4
After receiving this command, the chip will load in a 16-bit "data word" when 18 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.3.2.2 READ DATA
Programming Algorithm Requires Variable VDD
The PIC16C64X/66X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin." The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP VDDmin VDDmax = VCC range required during programming. = Minimum operating VDD spec for the part. = Maximum operating VDD spec for the part.
After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 18th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.3.2.3 INCREMENT ADDRESS
The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.3.2.4 BEGIN PROGRAMMING
Programmers must verify the PIC16C64X/66X at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C64X/66X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100 s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.3.2.5 END PROGRAMMING
After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time.
(c) 1997 Microchip Technology Inc.
DS30457A-page 7
PIC16C64X/66X
3.0 CONFIGURATION WORD
Note: The PIC16C64X/66X family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits. Parity bits for identification and configuration word must be clocked in/out, but are ignored and not checked.
FIGURE 3-1:
Bit Number: PIC16C642/662
CONFIGURATION WORD BIT MAP
15 CP1 14 CP0 13 CP1 12 CP0 11 CP1 10 CP0 9 MPEEN 8 BODEN 7 CP1 6 CP0 5 PWRTE 4 WDTE 3 FOSC1 2 FOSC0 1 P 0 P
bit 9:
MPEEN, Memory Parity Error Enable 1: Memory parity checking is enabled 0: Memory parity checking is disabled bit 7-6: CP1:CP0, Code Protect
Device PIC16C642/662 CP1 0 0 1 1 CP0 0 1 0 1 Code Protection All memory protected Upper 3/4 memory protected Upper 1/2 memory protected Code protection off
bit 8:
BODEN, Brown-out Enable bit 1 = Enables Brown-out 0 = Disables Brown-out PWRTE, Power-up Timer Enable bit 0 = Power up timer enabled 1 = Power up timer disabled WDTE, WDT Enable bit 1 = WDT enabled 0 = WDT disabled
bit 5:
bit 4:
bit 3-2: FOSC1:FOSC0, Oscillator Selection bit 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator bit 1-0: Parity bits for Configuration Word
DS30457A-page 8
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
4.0 CODE PROTECTION
4.1
The program code written into the EPROM can be protected by writing to the CP0 & CP1 bits of the configuration word. Note: Code protection should be the last test for a device, since the areas protected cannot be reprogrammed. Code protection is permanent for any device.
Programming Locations 0x000 to 0xFFF after Code Protection
For all PIC16C64X/66X devices, once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed.
4.2
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
PIC16C642 To code protect:
CONFIGURATION WORD
* Protect all memory * Protect upper 1/2 memory * Protect upper 3/4 memory * No code protection Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003) PIC16C662 To code protect: * Protect all memory * Protect upper 3/4 memory * Protect upper 1/2 memory * No code protection Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003)
0000001X00XXXXXX 101010XX10XXXXXX 010101XX01XXXXXX 1111111X11XXXXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
0000001X00XXXXXX 0101011X01XXXXXX 1010101X10XXXXXX 1111111X11XXXXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
(c) 1997 Microchip Technology Inc.
DS30457A-page 9
PIC16C64X/66X
4.3
4.3.1
Checksum
CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the PIC16C64X/66X memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0xFFF for the PIC16C662. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C64X/66X devices is shown in Table 4-2. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum.
The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums.
TABLE 4-2:
Device PIC16C642
CHECKSUM COMPUTATION
Code Protect OFF 1/2 3/4 ALL OFF 1/2 3/4 ALL Checksum* SUM[0x0000:0x0FFF] + (CONFIG & 0x3FFF) SUM[0x0000:0x07FF] + (CONFIG & 0x3FFF) + SUM_ID SUM[0x0000:0x03FF] + (CONFIG & 0x3FFF) + SUM_ID (CONFIG & 0x3FFF) + SUM_ID SUM[0x0000:0x0FFF] + (CONFIG & 0x3FFF) SUM[0x0000:0x07FF] + (CONFIG & 0x3FFF) + SUM_ID SUM[0x0000:0x03FF] + (CONFIG & 0x3FFF) + SUM_ID (CONFIG & 0x3FFF) + SUM_ID Blank Value 0x2FFF 0x52EE 0x41DE 0x30CE 0x2FFF 0x52EE 0x41DE 0x30CE 0x25E6 at 0 and Max Address 0xFBCD 0x04A3 0xF393 0xFC9C 0xFBCD 0x04A3 0xF393 0xFC9C
PIC16C662
Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
DS30457A-page 10
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
5.0 PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
TABLE 5-1:
Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. General P1 P2 P3 P4 P5 P6 P9 P8 VDDP IDDP VDDV VIHH1 VIHH2 IPP VIH1 VIL1 Supply voltage during programming Supply current (from VDD) during programming Supply voltage during verify Voltage on MCLR/VPP during programming Voltage on MCLR/VPP during verify Programming supply current (from VPP) (RB6, RB7) input high level (RB6, RB7) input low level 4.75 -- VDDmin 12.75 VDD + 4.0 -- 0.8 VDD 0.2 VDD 5.0 -- -- -- -- -- -- -- 5.25 20 VDDmax 13.25 13.5 50 -- -- V mA V V -- mA V V Schmitt Trigger input Schmitt Trigger input Note 1 Note 2 Sym. Characteristic Min. Typ Max. Units Conditions
Serial Program Verify P1 P2 P3 P4 P5 TR TF TSET1 THLD1 TDLY1 MCLR/VPP rise time (VSS to VHH) for test mode entry MCLR Fall time Data in setup time before clock Data in hold time after clock Data input not driven to next clock input (delay required between command/data or command/command) Delay between clock to clock of next command or data Clock to date out valid (during read data) Hold time after MCLR -- -- 100 100 1.0 -- -- -- -- -- 8.0 8.0 -- -- -- s s ns ns s
P6 P7 P8
TDLY2 TDLY3 THLD0
1.0 200 2
-- -- --
-- -- --
s ns s
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in Programming/Verify mode.
(c) 1997 Microchip Technology Inc.
DS30457A-page 11
PIC16C64X/66X
FIGURE 5-1:
VIHH MCLR/VPP P8 RB6 (CLOCK) RB7 (DATA) 1 100 ns 2 3 100 ns 0 4 5 P6 1 6 1 s min. 0 P5 1 s min. P3P4 } } 2 3 4 5 15
LOAD DATA COMMAND (PROGRAM/VERIFY)
0 P3
1
0
0
0
0
P4 100 ns min. Reset
100 ns min. Program/Verify Test Mode
FIGURE 5-2:
MCLR/VPP RB6 (CLOCK) RB7 (DATA) VIHH
READ DATA COMMAND (PROGRAM/VERIFY)
100ns 2 P6 1 6 1s min. 0 P7 P5 1s min. RB7 = output Program/Verify Test Mode RB7 input
P8
1
3 100 ns 1
4
5
2
3
4
5
15
0
0 P3
0
0
P4
100 ns min. Reset
FIGURE 5-3:
MCLR/VPP
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH P6 1 s min. Next Command 2
1 RB6 (CLOCK) RB7 (DATA) 0
2
3
4
5
6
1
1
1
0 P3 P4 100 ns min
0
0 P5 1s min.
0
0
Reset
Program/Verify Test Mode
DS30457A-page 12
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
NOTES:
(c) 1997 Microchip Technology Inc.
DS30457A-page 13
PIC16C64X/66X
NOTES:
DS30457A-page 14
(c) 1997 Microchip Technology Inc.
PIC16C64X/66X
NOTES:
(c) 1997 Microchip Technology Inc.
DS30457A-page 15
M
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All rights reserved. (c)1997, Microchip Technology Incorporated, USA. 8/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30457A-page 16
(c) 1997 Microchip Technology Inc.

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